1 . Field of the Invention
The present invention is directed generally to sample and hold circuits, and more specifically to sample and hold circuits which operate at very high frequencies. The present invention is also directed to a finite impulse response (FIR) filter which is constructed primarily of the sample and hold circuit disclosed herein.
2. Description of the Background
Sample and hold circuits are well-known circuits in the electrical art. In its simplest form, a sample and hold circuit samples a time varying input signal at a given point in time, and holds the sampled value of the input signal at an output terminal until instructed to release that value. Sample and hold circuits are often used to increase the duration of a signal for processing purposes. A sample and hold circuit can also be used for analog to digital conversion by repeatedly taking and holding samples of the time varying input signal. Often, several sample and hold circuits are provided in parallel to allow slow A/D operation and achieve a higher total sampling rate.
For the foregoing reasons, sample and hold circuits are extremely important. Such circuits often are found at the input end of complicated devices such as video receivers, radar signal processors, and medical imaging devices. As the ability of such devices to efficiently and quickly manipulate data increases, increased demands are made on the front end, i.e. the analog to digital converter, to operate at higher speeds.
Unfortunately, it is difficult to construct and operate known sample and hold circuits, at very high speeds (100 MHz). At very high speeds, sample and hold circuits are very difficult to implement because of the extremely high bandwidth which is required in the switch. Additionally, charge injection from the switch and the impact of jitter in the timing of clock pulse edges introduce errors which are unacceptable in high speed operations. Thus, the need exists for a sample and hold circuit which can accurately operate at very high speeds (100 MHz).